Buffers are used in a variety of applications where it is desirable to connect devices that are operating at different speeds, transfer rates and/or frequencies. In particular applications, such as a network environment, a number of buffers may have to be implemented for each of a number of separate channels in a particular network system. When first-in first-out (FIFO) buffers are implemented for each channel, the overall expense in increasing the depth of the buffers (i.e., each of the FIFOs) may result in device inefficiency.
An alternate implementation for a multi-channel memory may be to implement static random access memories (SRAMs) as the data buffers. An SRAM based buffer implementation requires a controller to maintain multiple software linked-lists of the entry stored for each of the channels that are stored in each of the SRAMs. The FIFO implementation also requires an intelligent controller to orchestrate the reading and writing of the channel buffers.
Since FIFO buffers are generally expensive, increasing the buffer size by adding more FIFO depth may not be cost effective. While the SRAM approach may be cheaper, increasing the overall buffer size by adding more SRAM devices may require a corresponding increase in the size of the linked-list in the controller unit. Furthermore, the memory assigned to each data buffer channel is fixed so sharing of unused storage capacity among the individual channels is not possible.